A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal-oxide-semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power logic systems. Tunnel field-effect transistors (TFETs) rely on quantum-mechanical tunnelling and, unlike conventional metal-oxide-semiconductor field-effect transistors (MOSFETs), require less than 60 mV of gate voltage swing to induce one order of magnitude variation in the drain current at ambient temperature. III-V heterostructure TFETs are promising for low-power applications, but are outperformed by MOSFETs in terms of speed and energy efficiency when high performance is required at higher drive voltages. Hybrid technologies-combining both TFETs and MOSFETs-could enable low-power and high-performance applications, but require the co-integration of different materials in a scalable complementary metal-oxide-semiconductor (CMOS) platform. Here, we report a scaled III-V hybrid TFET-MOSFET technology on silicon that achieves a minimum subthreshold slope of 42 mV dec(-1) for TFET devices and 62 mV dec(-1) for MOSFET devices. The InGaAs/GaAsSb TFETs are co-integrated with the InGaAs MOSFETs on the same silicon substrate by means of a CMOS-compatible replacement-metal-gate fabrication flow, allowing independent optimization of both device types.

Automated summary

The study presents a III-V hybrid TFET-MOSFET technology on silicon, achieving low-power and high-performance applications by optimizing InGaAs/GaAsSb TFETs and InGaAs MOSFETs simultaneously.