Journal
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
Volume 9, Issue 1, Pages 885-896Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JESTPE.2019.2955279
Keywords
Topology; Capacitors; Inverters; Switches; Power harmonic filters; Multilevel inverter (MLI) topology; phase opposing disposition pulsewidth modulation; reduced device count; symmetrical and asymmetrical topology; total blocking voltage (TBV)
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Funding
- Science and Engineering Research Board (SERB) through the Department of Science and Technology (DST), New Delhi, India [EMR/2017/00447]
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This article presents a single-phase symmetrical and asymmetrical multilevel inverter topology that can generate different levels of output voltage. The presented topology contains the least number of components compared to other topologies, reducing the size, complexity, and cost of the overall converter.
This article presents a single-phase symmetrical and asymmetrical multilevel inverter (MLI) topology. The presented topology can generate 9-level output voltage in a symmetrical configuration and 13- and 17-level output voltage in asymmetrical configuration with a single cell. The number of output levels can be improved further by increasing either the number of cells or switches in a single cell. The presented topology contains the least number of dc sources, semiconductor switches, capacitors, and diodes compared with classical and recently proposed topologies. Reduction in component count decreases the size, complexity, and cost of the overall converter. A detailed comparison has been done of the presented topology with the recently proposed topologies in terms of dc sources, semiconductor switches, capacitor, and total blocking voltage. Finally, to validate the presented concept, the prototype of the presented 9-, 13-, and 17-level MLI topologies has been tested in the laboratory for different switching frequencies, different modulation indexes, sudden load changes, and nonlinear load.
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