Journal
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
Volume 9, Issue 1, Pages 438-450Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JESTPE.2019.2954555
Keywords
Phase locked loops; Power conversion; Power system stability; Stability analysis; Circuit faults; Impedance; Converter; equal area criterion (EAC); low voltage ride through; phase-locked loop (PLL); synchronization stability; transient stability
Categories
Funding
- National Natural Science Foundation of China (NSFC) [61722307, U1510208]
- VILLUM FONDEN under the VILLUM Investigator Grant through the Center for Research on Microgrids (CROM) [25920]
- EPSRC [EP/T021713/1] Funding Source: UKRI
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This article studies the loss of synchronism (LOS) of VSCs during grid faults and proposes a variable structure PLL method to improve resynchronization capability. The method removes PLL's integral regulator during grid faults to eliminate its unfavorable effect, and experimental and simulation comparisons verify its performance.
Grid codes stipulate that grid-connected voltage source converter (VSC) interfaced generation units should possess fault ride-through capability during grid faults. Resynchronization with the postfault grid is crucial for this purpose. However, it is not always easy for VSCs connected to a high-impedance weak grid to achieve resynchronization during severe grid faults. This article studies the loss of synchronism (LOS) of VSCs during grid faults. A nonlinear model describing the dynamics of the phase-locked loop (PLL) is developed, and a modified equal area criterion is utilized to identify the crucial factor affecting the resynchronization. The findings show that PLL's integral regulator is unfavorable for the resynchronization since it probably causes the system operating point to enter negative damping zones and even reverse regulation zones, consequently resulting in LOS. A variable structure PLL method with great simplicity is proposed to improve the resynchronization capability. The method removes PLL's integral regulator during grid faults to eliminate its unfavorable effect. Experimental and simulation comparisons with existing methods verify the performance of the method.
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