Modulating tunneling width and energy window for high-on-current two-dimensional tunnel field-effect transistors

As a strong candidate for future electronics, tunnel field-effect transistors (TFETs) have attracted great attention recently due to their steep subthreshold swing and low power consumption. However, the low on-state current has been regarded as the major challenge toward high-performance (HP) applications. Herein, we propose a device architecture strategy to modulate the tunneling probability and achieve high on-state current taking boron phosphide (BP) 5-nm-gate TFETs as a case. By introducing different architectures and performing abundant simulation, a comprehensive study is performed to explore the intrinsic association between architecture and tunneling probability of 5 nm BP TFET. Particularly, derived from the effective modulation of tunneling width and energy window, 5 nm BP TFET with the spacer and pocket structures displays a large on-state current of 1506 mu A/mu m. Also, 5 nm BP TFET demonstrates the expected figures of merits for digital electronics and circuits compliant with the International Technology Roadmap for Semiconductors requirements for HP applications. Our findings will promote the development of 2D materials and device architectures for HP TFETs.

Automated summary

A device architecture strategy is proposed to modulate tunneling probability and achieve high on-state current in 5 nm boron phosphide TFETs. Through abundant simulation studies, it is found that BP TFETs with spacer and pocket structures can achieve a large on-state current.