A Novel Teeth Junction Less Gate All Around FET for Improving Electrical Characteristics

In this paper, we propose a novel Teeth Junctionless Gate All Around Field Effect Transistor (TH-JLGAA FET) based on gate engineering method, to obtain finer electrical characteristics. A 3 nm TH-JLGAA FET is designed and was scaled up to 14 nm to observe the effect of scaling on device performance. The characteristics are revealed and compared with contemporary JLGAA FETs. The results show that the novel TH-JLGAA FET appears to have finer Sub-thresholdSlope (SS), Drain Induced Barrier Lowering (DIBL), transconductance (g(m)), I-on/I-off current ratio and threshold voltage roll-off. Moreover, these remarkable characteristics can be controlled by engineering the structure and volume of the gate. In addition, the sensitivities of the novel TH-JLGAA FET device with respect to structural parameters are probed.

Automated summary

A novel Teeth Junctionless Gate All Around Field Effect Transistor (TH-JLGAA FET) is proposed in this paper, based on gate engineering method, to achieve finer electrical characteristics. The results show that the TH-JLGAA FET has superior performance compared to contemporary FETs and can be controlled by adjusting structural parameters.