Silicon nitride programmable photonic processor with folded heaters

General-purpose programmable photonic processors rely on the large-scale integration of beamsplitters and reconfigurable phase shifters, distributed within unit cells or photonic gates. With their future evolution threatened by several hardware constrains, including the integration density that can be achieved with current mesh topologies, in this work, we present a unit cell topology design to increase the integration density of waveguide mesh arrangements based on folded Mach-Zehnder Interferometers. We report the design details of a 40-unit cell waveguide mesh integrated in a 11 mm x 5.5 mm silicon nitride chip achieving, to the best of our knowledge, the highest integration density reported to date for a general-purpose photonic processor. The chip is electrically interfaced to a PCB and we report examples of reconfigurable optical beamsplitters, basic tunable microwave photonic filters with high peak rejection (40 dB approx.), as well as the dynamic interconnection and routing of 5G digitally modulated signals within the photonic mesh. (C) 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

Automated summary

This research introduces a new unit cell topology design to increase the integration density of photonic processors, achieving the highest integration density for waveguide mesh on a silicon nitride chip. The chip is electrically interfaced to a PCB, demonstrating reconfigurable optical beamsplitters, high peak rejection microwave photonic filters, and dynamic connection and routing of 5G digitally modulated signals within the photonic mesh.