Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems

In this paper, we present two novel approximate Full Adder cells with capacitive threshold logic (CTL) using carbon nanotube field-effect transistor (CNFET) technology. To investigate the efficiency of the proposed cells, extensive simulations are carried out at both application and transistor levels. At the application level, by using the MATLAB tool, the proposed cells are applied to the motion detector algorithm as one of the practical image processing applications. Peak signal-to-noise ratio (PSNR) is considered as a legitimate application-level evaluating factor. In addition, by using the HSPICE tool, the hardware level parameters such as average power consumption, delay, and power-delay product (PDP) are estimated. Then, a compromise between the application and hardware-level metrics is considered. Noise analysis is also accomplished by taking noise immunity curve (NIC) and average noise threshold energy (ANTE) into account. Furthermore, Monte Carlo transient analysis is exploited to study the robustness of the introduced cells against diameter deviations of the carbon nanotubes (CNTs). Simulation results indicate the supremacy of the proposed cells compared to others.

Automated summary

Two novel approximate Full Adder cells with capacitive threshold logic using carbon nanotube field-effect transistor technology are presented in this paper. Extensive simulations are carried out to investigate the efficiency of the proposed cells at both application and transistor levels. The results show the superiority of the proposed cells compared to others, considering a compromise between application and hardware-level metrics.