Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption

Bicubic interpolation is widely used in real-time image processing systems because of its quality. The real-time implementation of bicubic interpolation requires a lot of hardware resources, especially the number of multipliers because it represents high computational complexity. In this article, a set of algorithms that approximate the bicubic interpolation and reduce the hardware resource consumption are proposed. The proposed algorithms are based on combining linear and cubic interpolations. These algorithms are surveyed and compared in terms of interpolation quality, number of adders, number of multipliers, adaptive logic modules, lookup tables (LUTs), registers, and maximum operating frequency. These algorithms are implemented and tested on an Intel Cyclone V target. This article provides various choices of interpolation algorithms to cater to different application requirements, including accuracy, hardware resource consumption, and throughput performance. The implementation codes are available at github.com/DreamIP/Interpolation.

Automated summary

This article introduces a set of algorithms based on linear and cubic interpolations to approximate bicubic interpolation and reduce hardware resource consumption. The algorithms are surveyed and compared in terms of interpolation quality, hardware resource consumption, and other factors.