4.8 Article

A Short-Circuit Protection Circuit With Strong Noise Immunity for GaN HEMTs

Journal

IEEE TRANSACTIONS ON POWER ELECTRONICS
Volume 36, Issue 2, Pages 2432-2442

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2020.3013984

Keywords

Gallium nitride; HEMTs; MODFETs; Transient analysis; Logic gates; Switching circuits; Interference; Circuit optimization; gallium nitride high electron mobility transistors (GaN HEMTs); interference suppression; noise; protection

Funding

  1. National Natural Science Foundation of China [51777094]

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This article focuses on the interference mechanism of dv/dt noise on GaN HEMTs short-circuit protection circuits, proposing an improved solution by adding a discharging capacitor to enhance noise immunity. By optimizing key parameters, designers can evaluate the noise immunity of protection circuits with different parameters during the design processes.
Gallium nitride high electron mobility transistors (GaN HEMTs) show significant advantages in high frequency and high switching speed applications, which has gathered great interests. Due to the low short-circuit withstand capacity, the short-circuit protection with high response speed is critical for GaN HEMTs. Besides, the high switching speed of GaN HEMTs brings severe interference to protection circuits, which becomes a key obstacle for ultrafast short-circuit protection. This article analyzes the interference mechanism of dv/dt noise on the desaturation short-circuit protection circuits in detail. According to the noise propagation model, an improved protection circuit is proposed, in which a discharging capacitor is employed to enhance the noise immunity behavior. In addition, optimization methods of the key parameters are presented, which allow the designers to evaluate the noise immunity of the protection circuits with different parameters during the design processes. The experimental results show that the response time of the protection circuit is within 110 ns. Without the proposed methods, the noise introduced by a low dv/dt of 2.5 V/ns will generate false-trigger protection actions. The improved protection circuit can survive under the dv/dt up to 84 V/ns, which verifies the validity of the proposed optimization methods.

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