Cryogenic Characteristics of Multinanoscales Field-Effect Transistors

The cryogenic performance ofmultinanoscale CMOS transistors with a standard 55-nm Si-bulk technology is systematically investigated by dc measurements. In contrast to 300 K, the cryogenic drain saturation current (I-dsat) gain significantly enhances from 54% to 167% with the increasing channel length and has a relatively weak response to width change. In addition, the degraded sub-threshold swing (SS) due to the short channel effect is alleviated at lower temperatures. The merits of a typical nMOS transistor (W/L = 0.6 mu m/60 nm) worked at 4.2 K are associated with an improved I-dsat (similar to 1.3 times), decreased drain leakage current with three orders of magnitude, and 2/3 reduced SS. However, the cryogenic I-dsat tends to saturate below 10 K and the threshold voltage increases, aswell as barrier lowering inducedby drain voltage, starts to deteriorate. The detailed analyses on these MOSFET (deep) cryogenic characteristics are implemented based on the comprehensive semiconductor physics images, including energy band change, temperature/geometry-dependent scattering, band-to-band tunneling process, and depletion width influence. Our findings will be beneficial for the community to design ultralow temperature-integrated circuits.

Automated summary

The cryogenic performance of nanoscale CMOS transistors with a standard 55-nm Si-bulk technology was investigated through DC measurements. At lower temperatures, an increase in channel length significantly enhanced the cryogenic drain saturation current gain, while the response to width change was relatively weak. Additionally, the degraded sub-threshold swing due to the short channel effect was alleviated at lower temperatures.