Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures

Multiplication is one of the most extensively used arithmetic operations in a wide range of applications. In order to provide resource-efficient and high-performance multipliers, previous works have proposed different designs of accurate and approximate multipliers-mainly for ASIC-based systems. However, the architectural differences between ASICs- and FPGA-based systems limit the effectiveness of these multipliers for FPGA-based systems. Moreover, most of these multiplier designs are valid only for unsigned numbers. To bridge this gap, we propose a novel implementation technique for designing resource-efficient and low-power accurate and approximate signed multipliers which are optimized for FPGA-based systems. Compared to Vivado's area-optimized multiplier IPs, the designs obtained using our proposed technique occupy 47 to 63 percent less area (Lookup Tables). To accelerate further research in this direction and reproduce the presented results, the RTL and behavioral models of our proposed methodology are available as an open-source library.(1) 1. Online. [Available]: https://cfaed.tu-dresden.de/pd-downloads.

Automated summary

The study highlights the importance of multiplication in various applications, with accurate and approximate multiplier designs primarily proposed for ASIC systems. However, the architectural differences between ASICs and FPGA systems limit the effectiveness of these designs. A novel technique for designing signed multipliers optimized for FPGA systems is introduced to address this gap, offering improved efficiency and reduced power consumption.