4.6 Article

An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS

Related references

Note: Only part of the references are listed.
Article Engineering, Electrical & Electronic

A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE

Jinhyung Lee et al.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS (2018)

Article Engineering, Electrical & Electronic

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET

Jay Im et al.

IEEE JOURNAL OF SOLID-STATE CIRCUITS (2017)

Article Engineering, Electrical & Electronic

Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology

Jaeduk Han et al.

IEEE JOURNAL OF SOLID-STATE CIRCUITS (2016)