Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 68, Issue 2, Pages 622-626Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2020.3014925
Keywords
Decision feedback equalizers; Image edge detection; Hardware; Adaptive equalizers; Engines; Power demand; Receiver; DC offset; offset cancellation; mismatch; equalizer; DFE; summer; adaptation; adaptive equalizer
Categories
Funding
- Inter-University Semiconductor Research Center of Seoul National University
- Inchips Technologies, South Korea
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This research presents the design of a low-power receiver with an adaptive equalizer and an offset cancellation scheme. The proposed AOC engine and shared-half rate structure help achieve a BER of less than 10(-12) in a wide range of data rates. The prototype chip consumes 18.6 mW at 10 Gb/s and exhibits a figure-of-merit of 0.068 pJ/b/dB.
This brief presents the design of a low-power receiver (RX) with an adaptive equalizer and an offset cancellation scheme. The proposed adaptive offset cancellation (AOC) engine removes the random DC offset of the data path by examining the sampled data and edge outputs of a random data stream. In addition, a shared-summer decision-feedback equalizer in a half-rate structure is incorporated to reduce power dissipation and hardware complexity of the adaptive equalizer. A prototype chip fabricated in 40 nm CMOS technology occupies an active area of 0.083 mm(2). Thanks to the AOC engine, the proposed RX achieves the BER of less than 10(-12) in a wide range of data rates: 1.62-10 Gb/s. The proposed RX consumes 18.6 mW at 10 Gb/s over a channel with 27-dB loss at 5 GHz, exhibiting a figure-of-merit of 0.068 pJ/b/dB.
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