CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder

This paper proposes a carbon nanotube FET (CNFET)-based ultra-low-power dualVDD ternary half adder (HA) circuit. The proposed design utilizes both the available ternary power supply voltages (V-DD & V-DD/2) and prevents direct path between the power supplies and ground, thus significantly reducing the power dissipation as compared to the conventional designs. The performance of the proposed CNFET dual-VDD HA has been compared with the same circuit implemented with 45 nm MOSFETs and also with other CNFET-based state-of-the-art HA designs proposed in the literature. The proposed HA consumes merely 86 nW of power which is significantly lesser (6690% lower) than the power required by other ternary HA designs, and also exhibits 69-91% lower delays. The overall PDP of the proposed HA circuit is merely 4-11% of the PDP of corresponding CMOS ternary HA and other benchmarked CNFET HA designs.

Automated summary

This paper presents a carbon nanotube FET-based ultra-low-power dualVDD ternary half adder circuit, which significantly reduces power dissipation compared to conventional designs and has lower delays. The proposed design consumes significantly less power and exhibits lower delays compared to other CNFET and CMOS ternary half adder designs.