Layered CMOS SPADs for Low Noise Detection of Charged Particles

This paper reports the characterization of SPAD arrays fabricated in a 150 nm CMOS technology in view of applications to the detection of charged particles. The test vehicle contains SPADs with different active area and operated with different quenching techniques, either passive or active. The set of devices under test (DUTs) consists of single-tier chips, about 30 mm(2) in area, with dual-tier structures where two chips are face-to-face bump bonded to each other. In the dual-layer structure obtained in this way, the coincidence signal between overlapping SPAD pairs is read out, with a beneficial impact on the dark count noise performance. The DUT characterization was mainly focused on studying the breakdown voltage in the single-layer arrays and the dark count rate (DCR), measured in different working conditions, in both the single- and the dual-layer structures. Comparison between the DCR performance of the two configurations clearly emphasizes the advantage of the coincidence readout architecture.

Automated summary

This paper reports the characterization of SPAD arrays in a 150 nm CMOS technology for the detection of charged particles. The study focused on breakdown voltage and dark count rate (DCR) in both single- and dual-layer structures, highlighting the advantage of the coincidence readout architecture.