4.6 Article

Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits

Journal

ELECTRONICS
Volume 10, Issue 1, Pages -

Publisher

MDPI
DOI: 10.3390/electronics10010079

Keywords

multiple valued logic (MVL); resistive random access memory (RRAM); carbon nanotube field effect transistor (CNTFET); ternary logic systems; emerging technologies

Funding

  1. Yayasan Universiti Teknologi PETRONAS (YUTP)Fundamental Research Grant with cost centre [015LC0-245]

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The latest multiple valued logic circuits have shown potential for higher storage density compared to binary circuits, attracting attention for digital system designs. Carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) are considered suitable options for MVL circuit designs, with proposed designs demonstrating advantages in terms of reduced transistor count, decreased cell area, and lower power consumption. Additionally, the participation of RRAM provides non-volatility advantages.
The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

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