Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET

In this paper, we investigated the electrical coupling between the top and bottom transistors in a monolithic 3-dimensional (3D) inverter (M3INV) stacked vertically with junctionless field-effect transistor (JLFET), which is one of candidates to replace metal-oxide-semiconductor field-effect transistors (MOSFET). Currents, transconductances, and gate capacitances of the top N-type transistor at the different gate voltages of the bottom P-type transistor as a function of thickness of inter-layer dielectric (T-ILD) and gate channel length (L-g) are simulated using technology computer-aided-design (TCAD). In M3INV stacked vertically with MOSFET (M3INV-MOS) and JLFET (M3INV-JL), the variations of threshold voltage, transconductance, and capacitance increase as T-ILD decreases and they increase as L-g increases, and thus there is a strong coupling in M3INV at the range of T-ILD <= 30 nm. In M3INV, the coupling between stacked JLFETs in M3INV-JL is larger than that between MOSFETs in M3INV-MOS at the same T-ILD and L-g. The switching threshold voltage (V-m) and noise margins (NMs) of M3INV are calculated from the voltage transfer characteristics (VTC) simulated with TCAD mixed-mode. As the gate lengths of M3INV-MOS and M3INV-JL increase, the V-m variations increase and decrease, respectively. The smaller the gate lengths of M3INV-NOS and M3INV-JL, the larger and smaller the variation of V-m, respectively. The noise margin of M3INV-MOS is larger and better for inverter characteristics than one of M3INV-JL. M3INV-MOS has less electrical coupling than M3INV-JL.

Automated summary

In this paper, the electrical coupling between the top and bottom transistors in a monolithic 3D inverter (M3INV) stacked with JLFET was investigated. It was found that there is strong coupling in M3INV when T-ILD <= 30 nm. The noise margin of M3INV-MOS is larger and better for inverter characteristics than that of M3INV-JL.