Design of CMOS three-stage amplifiers for near-to-minimum settling-time

In this paper, we provide a new procedure that allows to design a generic three-stage amplifier from settling-time specifications. The procedure analyze the settling-time of pure twoor three-pole amplifiers (i.e., with no zeros) and extends the results to a generic amplifier that includes one or two zeros even placed in the right-half plane. The validity of the proposed approach is demonstrated through a design example of a three-stage CMOS amplifier suitable for switched-capacitor applications.

Automated summary

This paper introduces a new procedure for designing a generic three-stage amplifier based on settling-time specifications. The procedure extends the analysis of settling-time from pure two- or three-pole amplifiers to a generic amplifier with one or two zeros, even in the right-half plane. The validity of the proposed approach is demonstrated through the design example of a three-stage CMOS amplifier suitable for switched-capacitor applications.