4.2 Article

Design and Simulation of Reliable Low Power CMOS Logic Gates

Journal

IETE JOURNAL OF RESEARCH
Volume 69, Issue 2, Pages 1022-1032

Publisher

TAYLOR & FRANCIS LTD
DOI: 10.1080/03772063.2020.1847700

Keywords

Device scaling; DSM regime; low power VLSI; Monte-Carlo simulation; nanoscaled CMOS; stacking

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In this paper, a circuit-level reliable low leakage design methodology is proposed for integrated circuits. The proposed approach reduces leakage power significantly and improves the reliability of the circuits, as demonstrated through simulations and comparative experiments.
In this paper, a circuit-level reliable low leakage design methodology is proposed for integrated circuits (ICs). Low leakage circuit design is the most challenging research area for very large-scale integration (VLSI) circuit designers due to the increased demand of battery-operated portable systems. Leakage power is increasing continuously with each new technology node generation in deep sub-micron (DSM) regime. Large power dissipation harms the device characteristics and affects the overall performance of the circuits. Proposed approach is extensively discussed and verified for the low power operation and reliability. The various logic circuits are simulated and compared with the available leakage minimization techniques at 22 nm technology node using predictive technology model (PTM) bulk CMOS BSIM4 on HSPICE tool. Proposed approach reduces leakage power by approximate to 81% in XOR2 and XNOR2 gates as compared to conventional CMOS gates. Reliability of the nanoscaled circuits is affected by several device parameters. Process, voltage and temperature (PVT) variations, aging and radiation effects are considered for reliability testing. The reliability of the proposed approach is improved by 77.45% for power delay product (PDP) metric for the ring oscillator as compared to conventional circuit.

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