Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders

In video compression, throughputs of entropy encoders based on arithmetic coding are limited. This article presents the architecture of the entropy coder able to process in each clock cycle much more binary symbols than previous works. The architecture takes advantage of the multisymbol implementation of the binary arithmetic coder (BAC) developed earlier. To balance high throughputs of the BAC, fast implementations of binarization, context modeling, and probability model (PM) update are developed. The main improvement in the symbol rate stems from the decomposition of the processing path into many parallel ones. Critical paths associated with state transitions are shortened since each path updates the PM only for one context selected in each clock cycle. The negative impact on the symbol rate is compensated by the context-based symbol reordering. Although paths have variable bin/symbol rates, the applied buffering strategy improves the continuity of two data streams directed to the BAC, separately for context-coded and bypass-mode symbols. The entropy coder synthesized for the 90-nm TSMC technology consumes 273-k gates and operates at 570 MHz. It achieves the average symbol rate of 13.08 bins per clock cycle and the throughput of 7455 Mbins/s for high-quality H.265/HEVC compression.