4.8 Article

Multilevel Converters With Symmetrical Half-Bridge Submodules and Sensorless Voltage Balance

Journal

IEEE TRANSACTIONS ON POWER ELECTRONICS
Volume 36, Issue 1, Pages 447-458

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2020.3000469

Keywords

Multilevel converters; Bridge circuits; Capacitors; Semiconductor diodes; Switches; Batteries; Insulated gate bipolar transistors; Cascaded H-bridge (CHB); half-bridge; modular multilevel converter (MMC); multilevel converter; sensorless voltage balance

Funding

  1. National Science Foundation [1608929]

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This article proposes novel multilevel converters with symmetrical half-bridge submodules to reduce the number of active switch semiconductors and conduction losses. It also introduces a sensorless voltage balance scheme to eliminate capacitor voltage mismatch problems, greatly reducing capacitor voltage ripples and saving dc capacitances. Simulation and experimental results validate the superiority of the proposed multilevel converters and voltage balance scheme.
H-bridge-based multilevel converters (e.g., cascaded H-bridge converters) benefit from modularity and scalability. However, they suffer from the complexity and costs associated with a large count of semiconductor switches, together with their drivers and peripheral circuits, as well as higher conduction losses as compared to half-bridge-based counterparts, as two switches in each submodule must simultaneously conduct to provide a current path. To reduce the number of active switch semiconductors and conduction losses, this article proposes novel multilevel converters with symmetrical half-bridge submodules. The symmetrical half-bridge submodule features a bipolar voltage output, a reduced switch count, and simplicity. Furthermore, this article proposes a sensorless voltage balance scheme that successfully gets rid of capacitor voltage mismatch problems through diodes and submodule parallelization. This scheme can greatly reduce capacitor voltage ripples, thereby allowing the saving of dc capacitances, particularly in the case of numerous submodules. Finally, simulation and experimental results validate the superiority of the proposed multilevel converters and voltage balance scheme.

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