4.7 Article

High-Density Memristor-CMOS Ternary Logic Family

Journal

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2020.3027693

Keywords

Logic; memristor; multilevel; RRAM; ternary

Funding

  1. National Natural Science Foundation of China [61871429]
  2. Natural Science Foundation of Zhejiang Province [LY18F010012]

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This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family, showing significant improvements in data density and switching speed compared to conventional CMOS logic. The study systematically designs, simulates and experimentally verifies primitive logic functions, providing a promising foundation for practical implementations where high data density is critical.
This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

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