4.8 Article

Role of ALD Al2O3 Surface Passivation on the Performance of p-Type Cu2O Thin Film Transistors

Journal

ACS APPLIED MATERIALS & INTERFACES
Volume 13, Issue 3, Pages 4156-4164

Publisher

AMER CHEMICAL SOC
DOI: 10.1021/acsami.0c18915

Keywords

thin film transistors; oxide thin films; passivation; copper oxide; atomic layer deposition

Funding

  1. EPSRC [EP/P027032/1]
  2. PragmatIC Ltd.
  3. Royal Academy of Engineering [CIET 1819_24, RF/201718/1701]
  4. U.S. National Science Foundation (NSF) [DMR-2016453]

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High-performance p-type oxide thin film transistors (TFTs) have great potential for semiconductor applications, but often suffer from low hole mobility and high off-state currents. By applying a thin ALD Al2O3 passivation layer on the Cu2O channel and vacuum annealing, the TFT switching characteristics can be improved. Characterization by TEM-EDX and XPS shows that Al2O3 deposition on Cu2O reduces surface and forms a CuAlO2 interfacial layer. This, along with field-effect passivation, leads to improved TFT performance by reducing trap states and electron accumulation in the off-state.
High-performance p- type oxide thin film transistors (TFTs) have great potential for many semiconductor applications. However, these devices typically suffer from low hole mobility and high off-state currents. We fabricated p-type TFTs with a phase-pure polycrystalline Cu2O semiconductor channel grown by atomic layer deposition (ALD). The TFT switching characteristics were improved by applying a thin ALD Al2O3 passivation layer on the Cu2O channel, followed by vacuum annealing at 300 degrees C. Detailed characterization by transmission electron microscopy-energy dispersive X-ray analysis and X-ray photoelectron spectroscopy shows that the surface of Cu2O is reduced following Al2O3 deposition and indicates the formation of a 1-2 nm thick CuAlO2 interfacial layer. This, together with field-effect passivation caused by the high negative fixed charge of the ALD Al2O3, leads to an improvement in the TFT performance by reducing the density of deep trap states as well as by reducing the accumulation of electrons in the semiconducting layer in the device off-state.

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