Journal
MULTIMEDIA TOOLS AND APPLICATIONS
Volume 80, Issue 3, Pages 4263-4277Publisher
SPRINGER
DOI: 10.1007/s11042-020-09944-w
Keywords
Digital watermarking; FPGA implementation; Hardware-software co-simulation; LSB matching; Spatial domain; Visual information hiding
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The work proposes a technique for designing and implementing an information hiding scheme using hardware-software co-simulation, aiming to improve design verification efficiency and reduce development costs for DSP solutions. The scheme embeds information bits into the host image using the LSB matching technique, tested on a Spartan-3A DSP edition board and showing potential for application-specific events and low-cost hardware implementation through a graphical user interface.
The proposed work presents particulars of a technique for the design and hardware implementation of an information hiding scheme using hardware-software co-simulation. The methodology aims to improve the design verification efficiency, development time and cost for DSP solutions. The scheme represents architecture for visual information hiding framework where information bits embedded into the host image by means of LSB matching technique. The design is tested by targeting a Spartan-3A DSP edition board (XC3SD3400A-4FGG676C) and the simulated results illustrate that this architecture provides a better opening for application specific events as well as explores different areas concerned to low cost hardware implementation through a graphical user interface.
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