Journal
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Volume 67, Issue 9, Pages 7439-7450Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIE.2019.2942554
Keywords
Capacitors; Topology; Inverters; Stress; Switches; Discharges (electric); Power systems; Maximum voltage stress; multilevel; reduced active devices; self-voltage balance; step-up
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Funding
- National Natural Science Foundation of China [61573155, 51877085]
- Guangdong Natural Science Foundation [2016A03031358, 2018A030313066]
- Fundamental Research Funds for the Central University of SCUT [2018ZD50]
- Guangdong Key Laboratory of Clean Energy Technology
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In this article, the generalized symmetrical step-up multilevel inverter (MLI) using a single dc source and crisscross capacitor units (CCUs) is proposed. Compared with the conventional MLIs, the capacitor in each CCU can get self-voltage balance without auxiliary methods. The output level and boost factor of the proposed topology can be increased with fewer devices. And, importantly, its maximum voltage stress for the switching devices is limited below a low degree even though the peak output voltage increases. However, the maximum voltage stress of most other boost MLIs will rise badly with output voltage increasing. The abovementioned merits of the proposed topology in all show its suitability in renewable energy generation systems, distributed generation, and other applications of high power quality. The operation principles of the proposed MLI are fully described in the this article. The self-balance of capacitors is deduced based on the adopted modulation method. The capacitance calculation is also presented in detail. Afterward, the power loss of the proposed topology has been analyzed. And the comparative study illustrates its advantages on reduced active devices, lower voltage stress, boost ability, and self-balance against other MLIs. Finally, the simulation and the 1.2-kVA experimental prototype with two CCUs and 13-level output are implemented. The results verify the feasibility and performance of the proposed topology.
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