Journal
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Volume 67, Issue 10, Pages 8931-8935Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIE.2019.2951296
Keywords
Buffer; capacitorless; low-dropout regulator (LDO); low-V-DD structure; power supply rejection ratio (PSRR)
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Funding
- Sookmyung Women's University Research [11803-2013]
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To provide power to the latest mobile applications that use functions with heavy loads, in this letter, we present a capacitorless low-dropout regulator (LDO) that supplies a large load current up to 600 mA. The proposed buffer and the feedforward paths are used to provide a stable operation and fast response along with a large load current. Owing to these schemes, the proposed LDO has a high unity gain frequency of 2.85 MHz at 100 mA with a total compensation capacitance of 5.1 pF. In addition, the LDO operates under a wide input voltage range of 1.5-5.0 V owing to the low-V-DD structure. Also, a power supply rejection ratio was -52 dB at 100 kHz. The chip was implemented with a small size of 0.082 mm(2) using the I/O devices of a 0.18 mu m CMOS process with a minimum length of 0.5 mu m.
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