Journal
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Volume 67, Issue 9, Pages 8044-8053Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TIE.2019.2941135
Keywords
Insulated gate bipolar transistors; Field programmable gate arrays; Mathematical model; Integrated circuit modeling; Switching circuits; Computational modeling; Real-time systems; Field-programmable gate array (FPGA); hardware-in-the-loop (HiL); parallel structure; power electronic system modeling; real-time simulation
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Funding
- European Commission under Grant H2020 PANDA (H2020-LC-GV-2018)
- EU [824256]
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The field-programmable gate array (FPGA) based hardware-in-the-loop (HiL) test, which minimizes the time-step of the real-time simulation below 500 ns, is an enabling technology for the development of the control unit of high-power electronic systems (HPE). In order to improve the time performance of FPGA-based HiL, this article proposes a novel parallel structure using the predictive behavior of the power electronic system. With this structure, we design an improved system-level solver applied to HPE. A piecewise insulated-gate bipolar transistor (IGBT) model is used to determine the state of the switch, offering a quasi-realistic model of the power converter. A parallel integration method is also implemented to solve the status of the circuit elements. Moreover, the proposed parallel structural can execute both the IGBT model and circuit element model at the same time, thus, reducing the simulation time-step significantly. The numerical accuracy of the solution, the architecture design, and the issue of the parallel computation are discussed in detail. An ac-dc-ac topology is presented as a case study. At last, a 25 ns time step in the National Instruments FlexRIO platform is achieved. Results comparison with the reference model is also identified and discussed.
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