Impact of Varied Buffer Layer Designs on Single-Event Response of 1.2-kV SiC Power MOSFETs

In this article, the single-event response of the 1.2-kV silicon-carbide (SiC) power MOSFETs with varied buffer layer designs is investigated by the 2-D numerical simulations. The structural parameters of the buffer layers are compared and analyzed to understand the transient response after the heavy ion strike and the related physical mechanisms comprehensively. Simulation results reveal that an optimized single buffer structure can be acquired by using a relatively thicker buffer layer (T mu m) and a moderate doping concentration (D cm(-3)). It demonstrates that the single-event-burnout (SEB) performance can be improved significantly under the worst case bias conditions [a drain bias voltage of 1.2 kV and a linear energy transfer (LET) of 1 pC/mu m]. In addition, the optimized structural combinations adopted in the dual or triple buffer layers can strengthen the SEB performance further. The simulation results show that a step electric field distribution is established inside the optimized dual or triple buffers, where the electric field peak is mitigated from 3 to 2.2 MV/cm. Moreover, the excess carrier generation is suppressed and the local temperature rise is weakened during the transient electrothermal process. Consequently, the structure with the optimal buffer layer designs can enlarge the SEB safe operating area (SOA) from 30%-50% to 100% rated breakdown voltage at high LET bias, which makes the SiC power MOSFETs used in aerospace and aviation power electronic systems become possible.