Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 67, Issue 9, Pages 3729-3735Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2020.3011398
Keywords
Electrodes; Junctions; Tunneling; Semiconductor device modeling; Semiconductor device measurement; Switches; Substrates; Ferroelectric memories; ferroelectric tunnel junctions (FTJs); semiconductor device modeling
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Although metal/ferroelectric/semiconductor tunnel junctions have been attracting widespread interest as next-generation memory devices, only limited effort has been devoted so far to quantitatively address their current-voltage characteristics and their achievable memory window. In this article, we show experimental data on template Pt/BaTiO3/Nb:SrTiO3 tunnel junctions confirming, first of all, that large memory windows can be achieved in these devices when the switching of the electric polarization in the ferroelectric layer moves the substrate between an accumulation and a depletion condition. Besides, by measuring the current-voltage curve of the devices quickly after the set/reset pulses used for polarization switching, the importance of considering the detrimental effects of the large depolarization fields in the ferroelectric layer when assessing the device memory window is demonstrated. The experimental data are, then, reproduced by a model for electron transport through the junction accounting for both drift/diffusion and distributed tunneling in the semiconductor. The model allows to catch a comprehensive physical picture of device operation and represents a powerful tool for the design and optimization of ferroelectric tunnel junctions with semiconductor electrodes.
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