Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 67, Issue 9, Pages 3903-3907Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2020.3008882
Keywords
Deuterium; flash memory; gate resistance; gate-all-around(GAA); high-pressure (HP) annealing; oxide-nitride-oxide (ONO); oxide trap; RC delay; reliability; silicon nanowire; n(+) poly-Si gate-blocking oxide-charge trap nitride-tunneling oxide-silicon channel (SONOS); vertically stacked
Funding
- National Research Foundation (NRF) of Republic of Korea [2018 R1A2A3075302, 2019M3F3A1A03079603]
- IC Design Education Center (EDA Tool)
- National Research Foundation of Korea [4199990114709] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
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High-pressure (HP) deuterium (D-2) annealing was applied to a gate-all-around (GAA) MOSFET to improve device reliability and memory performance. The structure had gate dielectrics of oxide-nitride-oxide (ONO), which completely straddled vertically stacked multiple silicon nanowires (Si-NWs) with n(+) poly-Si gates. The HP D-2 annealing was effective for the vertically stacked GAA MOSFET as it was for a conventional planar MOSFET. In addition, the resistance of the n(+) poly-Si gate was also reduced after the HP D-2 annealing. This is attributed to the passivation of defects among adjacent poly-Si grains by the HP D-2. The reduced gate resistance (R-G) is advantageous for decreasing RC delay. Direct characterizations of dc I-V and analyses of ac low-frequency noise (LFN) supported the above mentioned behaviors.
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