An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration

This article presents a new analog circuit optimization system for automated sizing of analog integrated circuits. It consists of a genetic algorithm (GA)-based global optimization engine and an artificial neural network (ANN)-based local optimization engine. The key new idea is to use parallel computation to train ANN models for design space neighborhoods thus the local minimum search (LMS) can have a much faster search speed. For the GA-based global optimization, circuit performances are calculated by parallel SPICE simulations. For the LMS, circuit performance data are derived from ANN model predictions instead of SPICE simulations. Since the most time for an ANN-based LMS is spent on SPICE calls which can be run in parallel, the LMS process can also exploit the multiple core configuration of a modern computational server in addition to the GA global search. The fully parallelized optimization system is deployed to design a two-stage rail-to-rail operational amplifier and a fifth-order active-RC Chebyshev complex band-pass filter. The experimental results show that the proposed method provides about four times speed enhancement and comparable results compared with traditional approaches employing the same parallel global optimization but sequential SPICE calls during LMS.