Journal
IEEE ELECTRON DEVICE LETTERS
Volume 41, Issue 9, Pages 1428-1431Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2020.3011058
Keywords
Logic gates; Films; MESFETs; Annealing; Performance evaluation; Nickel; MESFET; perovskites; stannate; gate recess
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Funding
- Air Force Office of Scientific Research [FA9550-19-1-0245]
- National Science Foundation (NSF) through the University of Minnesota MRSEC [DMR-2011401]
- NSF [DMR-1741801]
- NSF through the National Nano Coordinated Infrastructure [ECCS-1542202]
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Fabrication of gate-recessed SrSnO3 (SSO) metal-semiconductor field-effect transistors (MESFETs) with Ni Schottky gates is reported on bi-layer epitaxial SSO films with a thin heavily-doped cap layer. Devices with 0.5-mu m gate length showed enhancement-mode behavior with a saturation drain current, IDSAT, of 33mA/mm and peak transconductance, g(m, max), of 65 mS/mm. The g(m, max) value is a roughly 2x improvement over control devices fabricated on single-layer films. Gate-recessed SSO MESFETs with Pt Schottky gates were also explored on the bi-layer films. Devices with 1-mu m gate length displayed I-DSAT = 133mA/mm and g(m, max) = 73 mS/mm, after thermal annealing.
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