Chaotic or Hyper-chaotic Oscillator? Numerical Solution, Circuit Design, MATLAB HDL-Coder Implementation, VHDL Code, Security Analysis, and FPGA Realization

Hyper-chaotic systems can exhibit a higher level of complexity in comparison with the chaotic systems. However, they require more resources when they are realized on a modular field-programmable gate array (FPGA). In this paper, we introduce full hardware/software comparison and security analysis of three-dimensional chaotic and four-dimensional hyper-chaotic oscillator systems. The two systems (previously implemented only in analog form) are realized on a modular FPGA hardware platform to generate high-speed random bit-streams. The realization is performed using two versions of VHDL code, one is generated automatically using a MATLAB HDL-Coder, and the optimized one which is manually written. The work explores the features of each oscillator system such as throughput, FPGA resources utilization, operating clock frequency, and security of the generated bit-streams, to show a compromise solution on these features. The experimental results show that the hyper-chaotic oscillator has higher level of security than the chaotic one, but it is slower and utilizes more FPGA resources. However, when the overall comparison measure figure of merit (FOM) is used, the chaotic system shows 188% better FOM than the hyper-chaotic system (for the automatically generated version) and 183% (for the manually written one).

Automated summary

This paper compares the hardware/software and security of three-dimensional chaotic and four-dimensional hyper-chaotic oscillator systems, finding that the hyper-chaotic system has higher security but is slower with more FPGA resource utilization, while the chaotic system shows better overall performance.