Journal
IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS
Volume 8, Issue 2, Pages 1584-1592Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JESTPE.2019.2909469
Keywords
Inductance; Topology; Capacitors; Inductors; High-voltage techniques; Switches; Zero current switching; Coupled inductors (CIs); dc-dc converter; high step-up; interleaved; nonisolation
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In this paper, a new topology to achieve ultrahigh step-up voltage conversion ratio and very low input current ripple is introduced for nonisolated high-power applications by using interleaved structure combined with coupled inductors (CIs) and switched capacitors. Using voltage lift capacitors in this topology not only recycles the energy related to leakage inductance of CIs and alleviates the voltage spike across the power switches but also increases the voltage gain of the converter. Moreover, utilizing CI structure provides zero-current switching (ZCS) turn-on condition for power switches and reducing the diodes reverses recovery losses and also improves the voltage gain of the converter. Using the interleaved structure in the low-voltage side noticeably decreases the input current ripple and current stress through magnetic elements. In addition, utilizing the voltage multiplier cell structure in the high-voltage side provides a high-voltage gain. The voltage stress across the power switches is considerably lower than the output voltage. Hence, the low-voltage-rated switches can be employed. Based on the mentioned advantages, the efficiency of this implementation is improved significantly. Finally, to validate the performance of the proposed converter, a 600-W, 24-V/520-V prototype circuit is implemented.
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