Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2Cylindrical Gate TFETs

In this work, an analytical model for current-voltage characteristics of a source pocket engineered stacked gate oxide SiO2/HfO(2)cylindrical gate all-around tunnel field effect transistor (CG TFET) has been developed. Source pocket length has been optimized in order to get higher ON-current and minimum subthreshold swing (SS). To model the surface potential in different regions, 2D Poisson's equation has been elucidated with adopting parabolic approximation formulation in cylindrical coordinates with appropriate boundary conditions. Tunneling current is calculated analytically by integrating the tunneling generation rate. The effect of source/channel and channel/drain depletion regions has been taken into consideration in proposed model for better accuracy. The modeled results have been verified with the numerical data from ATLAS (TM) 3D TCAD simulator.

Automated summary

An analytical model for current-voltage characteristics of a source pocket engineered stacked gate oxide SiO2/HfO(2) cylindrical gate all-around tunnel field effect transistor (CG TFET) has been developed in this work. The optimization of source pocket length is aimed at achieving higher ON-current and minimal subthreshold swing. The model takes into consideration the surface potential in different regions, tunneling current calculation, and the effects of source/channel and channel/drain depletion regions for better accuracy, which has been verified with numerical data from ATLAS (TM) 3D TCAD simulator.