Journal
NANOTECHNOLOGY
Volume 31, Issue 39, Pages -Publisher
IOP PUBLISHING LTD
DOI: 10.1088/1361-6528/ab9cf7
Keywords
ferroelectrics; interface engineering; low power; retention; scalability; tunnel-junctions
Funding
- NSF [ECCS 1610387]
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Ferroelectric random-access memories based on conventional perovskite materials are non-volatile but suffer from lack of CMOS compatibility, scalability limitation, and a destructive reading scheme. On the other hand, ferroelectric tunnel junctions based on CMOS compatible hafnium oxide are a promising candidate for future non-volatile memory technology due to their simple structure, scalability, low power consumption, high operation speed, and non-destructive read-out operation. Herein, we report an efficient strategy based on the interface-engineering approach to improve upon the tunneling electroresistance effect and data retention by depositing bilayer oxide heterostructure (Al2O3/Hf0.5Zr0.5O2) using atomic layer deposition (ALD) on Ge substrate which is treatedin-situALD chamber with H-2-plasma before film deposition. Integrating a thin ferroelectric layer i.e. Hf0.5Zr0.5O2(8.4 nm) with a thin interface layer i.e. Al2O3(1 nm) allowed us to reduce the operation (read and write) voltage to 1.4 V, and 4.3 V, respectively, while maintaining a good tunneling electroresistance or ON/OFF ratio above 10. Furthermore, an extrapolation to 1000 years at room temperature gives a residual ON/OFF ratio of 4.
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