Journal
NANOTECHNOLOGY
Volume 31, Issue 41, Pages -Publisher
IOP Publishing Ltd
DOI: 10.1088/1361-6528/ab9e90
Keywords
omega-gate nanowire field effect transistor; high-pressure deuterium annealing; multi-level random telegraph noise; low-frequency noise; trap analysis
Funding
- MOTIE (Ministry of Trade, Industry Energy) [10067808]
- KSRC (Korea Semiconductor Research Consortium)
- National Research Foundation of Korea (NRF) - KOREA government (MSIT) [2019R1F1A1060687]
- ASCENT European Nanoelectronics Network [87]
- CEA-LETI
- Korea Evaluation Institute of Industrial Technology (KEIT) [10067808] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
- National Research Foundation of Korea [22A20130012582, 2019R1F1A1060687] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
Ask authors/readers for more resources
In this work, we studied the effect of high-pressure deuterium annealing (HPDA) on a p-type omega-gate nanowire field effect transistor by random telegraph noise (RTN) signal analysis. After HPDA under conditions of 400 degrees C and 10 atm for 30 min, I(OFF)decreases by 41.2% and I(ON)increases by up to 5.4%. Also, subthreshold swing (SS) is reduced from 72 mV dec(-1)to 70 mV dec(-1). In RTN analysis, multi-level RTN is reduced to single-level RTN due to the passivation of a fast trap site by HPDA. Delta I-D/I(D)is also decreased 1.3 and 1.1 times at |V-OV| = 0.2 V and 0.4 V, respectively. From the low-frequency noise analysis, the reduction of trap density is observed by 86% at |V-OV| = 0.4 V after HPDA. Through these results, we found that the HPDA reduces traps of gate dielectric and improves the quality of the interface between gate dielectric and NW channel in p-type OGNW FET.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available