A novel low complexity and energy-efficient method to implement quaternary logic function in nanoelectronics

One of the main problems in chip design is the huge number of interconnections between digital blocks. Using Multi-valued logic can lead to the reduction of interconnections. So, the chip area and power dissipation in connections could be reduced. To fulfil the multi-valued logic aim, however, the number of transistors should be reduced considerably. In this paper, first, a novel quaternary multiplexer is designed. Then, a novel method for implementing the quaternary logic with single supply voltage is proposed. In this method, first, two binary functions are defined. One of them is activated when the quaternary function is '10 or '2'. Another one is activated when the quaternary function is '20 or '3'. These binary functions are implemented using the proposed multiplexer. Then, an encoder will create the quaternary function from these binary functions. The number of transistors for the quaternary full-adder designs is reduced from 195 in the previous works to 68 in the proposed method. Also, as the logics '10 and '20 are only produced in the last stage encoder, power consumption and PDP are considerably improved. The simulation results using HSPICE and 32 nm Stanford library confirm the correct operation and the considerable PDP improvement from 39.45% to 99.53%, as compared to the previous works.