Development of the Level-1 track trigger with Central Drift Chamber detector in Belle II experiment and its performance in SuperKEKB 2019 Phase 3 operation

The Level-1 trigger system (TRG) in the Belle II experiment is designed to summarize real-time sub-detectors information by using FPGA chips for the central data acquisition (DAQ) system, and it includes several sub-trigger systems for triggering various types of physics events in interest. The main focus in this report is CDCTRG: the track trigger system with Central Drift Chamber (CDC) detector, which is responsible for the real-time trajectory reconstruction of charged particles with various algorithms: Track-Segment Finder, 2D, 3D, Neuro-3D, and short tracking. CDCTRG is necessary for specific types of physics, such as hadronic and mu pair. This paper will introduce the design of the hardware system and algorithm implementation in FPGAs. Development, validation and performance of each CDCTRG module during SuperKEKB beam collision operation will also be discussed in detail.