Journal
JAPANESE JOURNAL OF APPLIED PHYSICS
Volume 59, Issue 7, Pages -Publisher
IOP PUBLISHING LTD
DOI: 10.35848/1347-4065/ab9e7d
Keywords
junctionless transistor; polycrystalline silicon; gate-all-around nanowire; steep subthreshold slope
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Funding
- Ministry of Education, Culture, Sports, Science, and Technology
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Junctionless p-type polycrystalline silicon (poly-Si) nanowire (NW) transistor with ideal subthreshold slope (SS) is successfully demonstrated by a gate-all-around channel structure and improved fabrication processes with highly suppressed grain boundary defects in the poly-Si. The fabricated devices, whose NW width is 9.6 nm, exhibit nearly ideal SS of 60 mV dec(-1)at room temperature. Furthermore, relatively high field effect mobility, small device-to-device SS variations and negligible temperature dependence are observed, indicating the device is promising for future three-dimensional integration.
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