Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 28, Issue 7, Pages 1736-1739Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2020.2995094
Keywords
Through-silicon vias; Maintenance engineering; Hardware; Redundancy; Circuit faults; Very large scale integration; 3-D integrated circuit (3-D IC); clustered faults; redundancy architecture; repair rate; through silicon via (TSV)
Funding
- National Natural Science Foundation of China [61904001, 61904047, 61974001, 61874156, 61874163, 61674048, 61834006]
- National Science and Technology Major Project [2017ZX01032-101]
- Anhui Provincial Natural Science Foundation [1908085QF272]
- Key Projects of Natural Science Research of Universities in Anhui Province [KJ2019A0163]
- Anhui Polytechnic University Research Startup Foundation [2018YQQ007]
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In this brief, a cobweb-based redundant through-silicon-via (TSV) design is proposed with efficient hardware as well as high repair rate to repair clustered faulty TSVs (FTSVs). The experimental simulation results demonstrate that for highly clustered faults, the repair rate of the proposed RTSV method is 48.59% and 1.75% higher than that of the ring-based and router-based RTSV methods, respectively. Furthermore, the proposed design can achieve 63.93% and 16.34% hardware reductions compared with the router-based and the ring-based design, respectively.
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