4.6 Article

Impact of Electrical Stress on Defect Generation in Thin GeO2/Ge Gate Stacks Fabricated by Thermal Oxidation

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 67, Issue 6, Pages 2516-2521

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2020.2989247

Keywords

Defects generation; fix charge; GeO2; germanium; slow trap

Funding

  1. Zhejiang Provincial Natural Science Foundation of China [LR18F040001]
  2. Fundamental Research Funds for the Central Universities

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The impact of electrical stress on the defect generation behaviors in thin GeO2/n-Ge gate stacks has been investigated through the measurement of the time-dependent dielectric breakdown (TDDB) and the stress-induced leakage current (SILC) characteristics. A multiple-spot breakdown (BD) event is confirmed, as well as a larger SILC generation probability compared with that in SiO2/Si structures. It is found that the slow trap generation is dominant by the amount of injected electron fluence (Q(inj)), and the fix charge generation is attributed to both Qinj and GeO2 thickness.

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