Journal
IEEE ELECTRON DEVICE LETTERS
Volume 41, Issue 8, Pages 1161-1164Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2020.3004716
Keywords
Vertical; nanowire; InAs; InGaAs; MOSFET; TLM
Categories
Funding
- Swedish Research Council
- Knut and Alice Wallenberg Foundation
- Swedish Foundation for Strategic Research
- European Union H2020 Program INSIGHT [688784]
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Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to L-g = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate g(m) = 3.1 mS/mu m and R-on = 190 mu m. This is the highest g(m) demonstrated on Si. Transmission line measurement verifies a low contact resistance with R-C = 115 Omega mu m, demonstrating that most of the MOSFET access resistance is located in the contact regions.
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