Physically Consistent Method for Calculating Trap-Assisted-Tunneling Current Applied to Line Tunneling Field-Effect Transistor

The default trap-assisted-tunneling (TAT) modeling framework, also known as the dynamic nonlocal TAT model, does not allow to specify multiple trap levels; the lone trap level allowed by the model is not considered in the Poisson-charge self-consistent loop. A method is presented here which allows specifying a trap distribution and the electrostatic degradation (ESD) caused by the trap distribution. The method relies on an individual simulation for each trap level in the distribution, with the total TAT current obtained by summing the TAT currents from the individual trap-level simulations. I-ds-V-gs data for an experimental L-shaped tunneling field-effect-transistor (LTFET) were fit using the proposed method, for validation of the proposed method. ESD was found to be an important factor in determining the TAT generation rate (G(TAT)). The calculated TAT current resulting from a trap distribution allowed to realistically estimate the lifetime parameter, which, if calculated based on a single trap, would be significantly underestimated. From the device point-of-view, this work demonstrates the severity of the TAT problem; TAT was found to dominate for the entire V-gs range, including the ambipolar current, and for all V-ds bias values.