A Fast-Settling Integer-N Frequency Synthesizer Using Switched-Gain Control

This paper presents a fully-integrated integer-N frequency synthesizer that uses switched-gain control (SGC) within the phased-locked loop (PLL). Unlike other methods to improve PLL performance, the SGC method exploits the potential advantages of positive feedback within the main loop. The proposed SGC-PLL uses a supervisor with four switching regions in the phase plane to minimize the effects of circuit non-linearity within the PLL. This results in significantly lower settling time than conventional designs while maintaining similar phase noise. The design has been implemented in the UMC 180 nm CMOS process for an output frequency range of 1-16 MHz. Test results show that the proposed approach decreases the settling time by a maximum of 24.7% compared to a conventional PLL with the same loop parameters.