Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 67, Issue 4, Pages 1149-1157Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2019.2941956
Keywords
Voltage controlled oscillator (VCO); current-to-digital converter; noise shaping; continuous-time Delta Sigma; current-reuse
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Funding
- Semiconductor Research Corporation (SRC) through The University of Texas at Dallas' Texas Analog Center of Excellence (TxACE) [2712.020]
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A continuous-time (CT) second-order Delta Sigma current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator which results in significant power and noise reduction compared to previous prototype. Excess loop delay in the proposed CDC is countered through judicious selection of loop parameters and no auxiliary DAC is used for loop delay compensation. A prototype CDC is implemented in 65nm CMOS and achieves 76dB dynamic range at a bandwidth of 0.2MHz from 1V supply with a walden FoM of 48fJ/step which is 9x improvement on the state-of-the-art.
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