Journal
IEEE PHOTONICS TECHNOLOGY LETTERS
Volume 32, Issue 12, Pages 673-676Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LPT.2020.2991672
Keywords
Micro-LED; wafer bonding; glass backplane; light extraction
Funding
- National Key Research and Development Program of China [2016YFB0401700]
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In an earlier study micro-LED micro display (<1 inch) on silicon CMOS backplane was demonstrated for augmented reality (AR) applications. Here we report the feasibility of wafer-level monolithic integration of micro-LEDs on glass substrate/backplane. Such issues as the cracking of GaN epitaxial layer, the deviation of alignment, and the peeling of insulator are discussed. SU-8 is proposed as the insulator material in vertical micro-LEDs, resulting into improved light extraction efficiency and allowing for the reduced light crosstalk between sub pixels if the integrated reflective mirrors are used. A directly driven micro-LED parallel array with a resolution of 320 x 720 with individual LED size ranging from 5 mu m to 28 mu m is demonstrated. It is believed that this monolithic technology on glass will play an important role in future high performance and low cost wearable and/or phone displays.
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