Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 55, Issue 4, Pages 1064-1076Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2019.2963589
Keywords
Amplitude phase shift keying (APSK); analog-to-digital converter (ADC); blocker tolerance; direct RF sampling; nonlinear distortion; phase noise; polar receiver; quadrature amplitude modulation (QAM); RF-to-digital converter (RDC); sub-sampling; time-to-digital converter (TDC)
Categories
Funding
- Global Foundries
- Intel Labs
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This article presents a direct RF-to-digital converter (RDC) for polar receivers, in which the amplitude information of the received signal is detected by a reconfigurable analog-to-digital converter (ADC) and its phase is digitized using a time-to-digital converter (TDC). The RDC prototype also includes a multi-phase reference generator and an ADC sampling position adjustment unit realizing the sub-sampling technique. Unlike conventional direct-RF sampling receivers, the proposed RDC samples the input RF signal at the baseband rate. The RDC is capable of digitizing a variety of modulation waveforms, such as quadrature amplitude modulation (QAM), phase shift keying (PSK), and amplitude phase shift keying (APSK). When comparing QAM to APSK, the later has advantages of relaxed system requirements on phase noise and linearity. The proposed direct RF-to-digital polar converter IC achieves a maximum data rate of 1.94 GB/s with a 1024-APSK modulation at a carrier frequency of 6 GHz, while consumes only 3.8 mW power under 1.1 V supply.
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