Journal
IEEE ELECTRON DEVICE LETTERS
Volume 41, Issue 4, Pages 637-640Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2020.2972439
Keywords
3D integration; fully depleted (FD); silicon-on insulator (SOI); irradiation; total ionizing dose (TID); low-frequency noise
Categories
Funding
- DTRA Basic Research Program on 3D Integration Research [HDTRA 1-18-1-0002]
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Effects of additional thermal budget associated with a three-dimensional (3D) fabrication sequence are evaluated for the total-ionizing dose radiation response of fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Current-voltage and low-frequency (1/f) noise measurements are compared for (1) conventional planar FD-SOI MOSFETs, and (2) MOSFETs formed in the bottom layer of the 3D process and subjected to the process steps associated with formation of a second active layer. Similar radiation-induced voltage shifts and increases of 1/f noise are observed after irradiation for both types of structures. These similar changes in response show that the additional thermal processing involved with 3D fabrication has little effect on border-trap densities and radiation-induced charge trapping in gate and/or buried oxides of MOSFETs formed in the bottom layer of the 3D process.
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