Journal
ELECTRONICS LETTERS
Volume 56, Issue 16, Pages 803-805Publisher
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/el.2020.0344
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Funding
- National Natural Science Foundation of China [61704050]
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This Letter proposes a reliable and lightweight key generator based on a novel bit-self-test arbiter physically unclonable function (BST-APUF). The BST-APUF adds a delay detection circuit into a classical APUF to automatically test the delay deviation that produces each bit of the PUF response and generates a reliability-flag for each response to indicate its reliability. The key generator collects robust responses and produces a secure key using a cryptographic entropy accumulator. FPGA implementation results show that the overhead and the helper data length of the authors proposed key generator are significantly lower than that of the state-of-the-art schemes when generating a 128-bit key with a bit error rate of 10(-9).
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